1. Field of the Invention
The present invention relates to a fabrication method of a multilayer Printed Wiring Board (PWB) and more particularly, to a fabrication method of a multilayer PWB having surface via holes covered with mounting pads.
2. Description of the Prior Art
A multilayer PWB is typically comprised of two or more subboards laminated with at least one prepreg layer intervening between two adjacent ones of the subboards Each of the subboards is formed by a dielectric substrate and a conductive pattern fixed on one side of the dielectric substrate or two conductive patterns fixed on both sides thereof.
Usually, the conductive patterns of the subboards are electrically interconnected with one another through plated holes penetrating at least one of the subboards and having metal-plated inner walls. An outermost one or two outermost ones of the conductive patterns constitute a predesigned outer circuit or circuits. The remainder of the conductive patterns constitute a predesigned inner circuit or circuits.
To mount surface-mounting electronic components on the Multilayer PWB, mounting pads are provided on the outermost one or two outermost ones of the conductive patterns serving as the outer circuit or circuits.
Some of the plated holes penetrate entirely the multilayer PWB itself from one side to another to electrically interconnect the outer circuit or circuits with some of the inner circuits, which are termed "plated through holes". The plated holes that do not penetrate entirely the multilayer PWB itself from one side to another are termed "plated via holes".
Especially, the plated via holes that penetrate only the outermost one of the laminated subboards to electrically interconnect the outer circuit and a next one of the inner circuits are termed "plated surface via holes".
In recent years, to increase the mounting density of electronic components on a multilayer PWB, mounting pads have been placed not only on the outer circuit or circuits but also on the plated surface via holes. In this case, the plated surface via holes are closed by the mounting pads; in other words, the opening mouths of the plated surface via holes are padded with the mounting pads. Therefore, these via holes may be termed "padded, plated surface via holes".
Multilayer PWBs with padded, plated surface via holes have been becoming practically used more and more widely because of their advantage of the increased mounting density.
FIG. 1 shows a flow chart of a conventional fabrication method of a multilayer PWB with padded, plated surface via holes. FIG. 2 shows a part of a multilayer PWB fabricated by this conventional method.
As shown in FIG. 2, a multilayer PWB 101 is comprised of first and second double-sided copper-clad laminates 110 and 120 serving as first and second subboards, and an intervening prepreg layer 130 between the first and second laminates 110 and 120.
The first copper-clad laminate 110 is formed by a dielectric substrate 111, a patterned outer copper foil 112 on the outer side of the substrate 111, and a patterned inner copper foil 113 fixed on the inner side thereof. Holes 116a are formed to penetrate the substrate 111 and the outer and inner copper foils 112 and 113.
Plated copper layers 114 are formed on the outer and inner copper foils 112 and 113 and the inner walls of the holes 116a, respectively. The parts of the plated copper layers 114 formed on the inner walls of the holes 116a serve to electrically interconnect the outer copper foil 112 with the opposing inner copper foil 113. The holes 116a whose inner walls are covered with the copper layers 114 constitute plated surface via holes 116.
The patterned outer copper foil 112 and the parts of the copper layers 114 located thereon constitute a first outer circuit 117. The patterned inner copper foil 113 and the parts of the copper layers 114 located thereon constitute a first inner circuit 118, which is electrically connected to the first outer circuit 117 through the plated surface via holes 116.
Plated copper layers 115, which serve as mounting pads, are formed on the parts of the plated copper layers 114 located over the outer copper foil 112 (i.e., located on the first outer circuit 117).
The second copper-clad laminate 120 is formed by a dielectric substrate 121, a patterned outer copper foil 122 fixed on the outer side of the substrate 121, and a patterned inner copper foil 123 fixed on the inner side thereof. Holes 126a are formed to penetrate the substrate 121 and the outer and inner copper foils 122 and 123.
Plated copper layers 124 are formed on the outer and inner copper foils 122 and 123 and the inner walls of the holes 126a, respectively. The parts of the plated copper layers 124 formed on the inner walls of the holes 126a serve to electrically interconnect the outer copper foil 122 with the opposing inner copper foil 123. The holes 126a whose inner walls are covered with the copper layers 124 constitute plated surface via holes 126.
The patterned outer copper foil 122 and the parts of the copper layers 124 located thereon constitute a second outer circuit 127. The patterned inner copper foil 123 and the parts of the copper layers 124 located thereon constitute a second inner circuit 128, which is electrically connected to the first outer circuit 127 through the plated surface via holes 126.
Plated copper layers 125, which serve as mounting pads, are formed on the parts of the plated copper layers 124 located over the outer copper foil 122 (i.e., located on the second outer circuit 127).
A hole 131a is formed to penetrate the first and second-copper-clad laminates 110 and 120 (i.e., the first and second subboards) and the intervening prepreg layer 130. A plated copper layer 132 is formed on the corresponding parts of the plated copper layers 114 and 124 of the first and second laminates 110 and the inner wall of the hole 131a. the part of the plated copper layer 132 located on the inner wall of the hole 131a serves to electrically interconnect the outer copper foil 112 of the first laminate 110 with the outer copper foil 122 of the second laminate 120. The hole 131a whose inner wall is covered with the plated copper layer 132 constitutes a plated through hole 131.
The multilayer PWB 101 shown in FIG. 2 is fabricated in the following way.
As shown in FIG. 1, first, the first and second copper-clad laminates 110 and 120, which have been cut to have a desired same size, are prepared (step S1).
Next, the holes 116a are formed by drilling to penetrate the first laminate 110, and the holes 126a are formed by drilling to penetrate the second laminate 120 (step S2).
Then, the first and second copper-clad laminates 110 and 120 are subjected to panel electroplating of copper. Thus, the copper layers 114 are formed on the outer and inner copper foils 112 and 113 and the inner walls of the surface via holes 116a of the first laminate 110, and the outer and inner copper foils 122 and 123 and the inner walls of the surface via holes 126a of the second laminate 120, respectively (step S3).
Photoresist films are formed on the inner copper foil 113 of the first laminate 110 and the inner copper foil 123 of the second laminate 120, respectively. Then, the photoresist films are exposed and developed, thereby forming etching masks on the inner copper foil 113 of the first laminate 110 and the inner copper foil 123 of the second laminate 120, respectively (step S4).
Using the etching masks thus formed, the inner copper foil 113 of the first laminate 110 and the inner copper foil 123 of the second laminate 120 are selectively etched using an etching solution such as a water solution of copper chloride. The etching masks are then removed (step S5).
Through the above process steps S1 to S5, the first and second subboards 110 and 120 are prepared. The first subboard 110 has the patterned inner copper foil 113, the unpatterned outer copper foil 112, and the plated holes 116. The second subboard 120 has the patterned inner copper foil 123, the unpatterned outer copper foil 122, and the plated holes 126. The plated holes 116 and 126 will become plated surface via holes after lamination.
Subsequently, the first and second subboards 110 and 120 and the prepreg layer 130 are stacked so that the patterned inner copper foils 113 and 123 are opposite to one another and the prepreg layer 130 is sandwiched by the first and second subboards 110 and 120. Release films are applied onto the outer copper foils 112 and 122 of the first and second subboards 110 and 120, respectively (step S6).
The first and second subboards 110 and 120 and the prepreg layer 130 thus stacked are placed between upper and lower platens of a laminating machine so that the release film applied onto the second subboard 120 is contacted with the lower platen and the release film applied onto the first subboard 110 is contacted with the upper platen. Then, the stack of the first and second subboards 110 and 120 and the prepreg layer 130 is pressed by lowering the upper platen under heat for a preset period, thereby joining them together. Thus, a laminated board is given, which is comprised of the first and second subboards 110 and 120 and the prepreg layer 130 (step S7).
A typical lamination temperature is approximately 170.degree. C., a typical lamination pressure is 8 to 25 atoms, and a typical lamination time is approximately two hours.
During this lamination step, a synthetic resin contained in the prepreg layer 130 is melted due to the applied heat and then, it is slightly pushed or flown out of the holes 116 and 126 of the first and second subboards 110 and 120 due to the applied pressure. The resin of the prepreg layer 130 thus pushed out is cured after the laminated board is cooled down.
After removing the release films from the top and bottom of the laminated board, the top and bottom of the laminated board are planarized to remove the cured, pushed-out resin of the prepreg layer 130 using a belt sander (step S8).
Following this planarizing process, the hole 131 is formed by drilling to entirely penetrate the laminated board itself (step S9).
The laminated board is then subjected to panel electroplating of copper, thereby forming the copper layers 115, 125, and 132 on the plated copper layers 114 and 124 and the inner wall of the hole 131a. The copper-plated via holes 116 and 126 are closed by the plated copper layers 115 and 125, respectively (step S10).
Photoresist films are formed on the top and bottom of the laminated board, respectively. Then, the photoresist films are exposed and developed, thereby forming etching masks on the top and bottom of the laminated board, respectively (step S11).
Finally, using the etching masks thus formed, the outermost copper layers 115 and 116 are selectively etched by an etching solution such as a water solution of copper chloride. Thus, the plated copper layers 115 and 125 are patterned. After removing the etching masks, the top and bottom of the laminated board are subjected to surface finishing, resulting In the multilayer PWB 101 shown in FIG. 2 (step S12).
With the conventional fabrication method as explained above, however, the adhesion or bonding strength between the plated copper layers (or, mounting pads) 115 and 125 and the cured resin of the prepreg layer 130 located in the surface via holes 116 and 126 is not sufficiently high. As a result, there is a problem that the plated copper layers or mounting pads 115 and 125 tend to be apart from the cured resin of the prepreg layer 130 during a mounting or soldering process of surface-mounting electronic components. The possibility of this problem becomes higher as the diameter of the surface via holes 116 and 126 increases.
It is supposed that this problem is caused by the following reason.
Because the cured resin of the prepreg layer 130 pushed out of the surface via holes 116 and 126 during the lamination step S7 is polished with the use of a belt sander in the step S8, the exposed surface of the remaining resin is planarized. The planarized surface of the resin is difficult to be roughened by any conventional preprocess of the panel plating step S10. Accordingly, the anchor effect between the remaining resin of the prepreg layer 130 and the plated copper layers or mounting pads 115 and 125 does not become sufficiently strong.
The Japanese Non-Examined Patent Publication No. 1-241895 published in September 1989 discloses a fabrication method of a multilayer PWB with blind through holes In this method, a patterned copper layer is left on the mouth of a surface via hole by etching and therefore, the mouth of the surface via hole Is flattened due to existence of the patterned copper layer. However, no roughening technique for a cured resin of a prepreg layer is disclosed in this Publication.
The Japanese Non-Examined Patent Publication No. 5-343846 published in December 1993 discloses a fabrication method of a PWB with padded surface via holes. In this method, the exposed surface of a cured resin of a prepreg layer located in a surface via hole is planarized by polishing. However, no roughening technique for a cured resin of a prepreg layer is disclosed in this Publication also.
On the other hand, the following surface-roughening methods (i) to (iv) have been developed to Increase the adhesion or bonding strength between a plated copper layer and a cured resin of a prepreg layer located in a surface via hole.
(i) An embossed release film is used to transfer the bosses of the release film to a cured resin of a prepreg layer located in a surface via hole. The bosses of the release film are transferred to the contacted area of the resin during a lamination step, resulting in the roughened surface of the resin. PA1 (ii) The surface of a cured resin of a prepreg layer is roughened by mechanical polishing using a belt sander or the like. PA1 (iii) The surface of a cured resin of a prepreg layer is roughened by colliding hard particles such as a sand using a sand blasting machine or the like. PA1 (iv) The surface of a cured resin of a prepreg layer is chemically swollen and then, it is etched using a water solution of alkali permanganate, resulting in the roughened surface of the resin.
However, all the surface-roughening methods (i) to (iv) are unable to realize a satisfactorily-high adhesion or bonding strength.